1. Field of Invention
The present invention relates to a semiconductor packaging substrate and a process for producing the same. More specifically, the present invention relates to a semiconductor substrate that can be used in flip-chip ball grid array packaging.
2. Description of Related Art
Flip chip packaging has been a popular packaging technology. In flip chip packaging, bump pads are arranged in area array on an active surface of a chip. Bumps are formed on the corresponding bump pads to electrically connect the chip to the carrier. Flip chip packaging has many advantages such as reduced package area, increased package density, and reduced signal path. A rigid substrate is usually used as a packaging carrier, because it can provide high-density and high-pin-count layout. Generally, the rigid substrate is formed by lamination or build-up.
In the rigid substrate lamination process, more than one single-sided or double-sided sheets having copper foil thereon are provided. Each of the copper foils is patterned to form a patterned metal layer. A bonding sheet is interposed between the sheets and bonded with them by thermal compression. Then, mechanically drilling and plating processes are sequentially performed to form plating through holes (PTH) though the sheets for electrically connecting the metal layers.
In the rigid substrate build-up process, insulation layers and patterned metal layers are sequentially formed on an insulated core base. The metal layers are electrically connected to one another by at least one contact via. The contact via is formed by forming a through hole in the insulation layers and the patterned metal layers and then plating to fill the through hole. Forming the through hole is achieved by non-mechanically drilling process such as photo-via forming, laser ablating and plasma etching.
FIG. 1 is a schematic, cross-sectional view of a conventional flip-chip ball grid array packaging substrate obtained by build-up technology. The packaging substrate 100 has a core 110 having copper foils on both sides thereof as a base. The copper foils are patterned to form metal layers 112 on both sides of the base. Mechanically drilling and plating processes are sequentially performed to form vias 114 for electrically connecting with the metal layers 112. Insulation layers 120a are respectively formed on the metal layers 112. Then, each of the insulation layers 120a is subject to non-mechanically drilling such as photo-via forming, laser ablating and plasma etching to form a first opening therein, respectively. A plating process is performed to form a via 140a in each of the first openings and form metal layers 130a respectively on the insulation layers 120a. The metal layers 130a are electrically connected to the metal layers 112 through the vias 140a. Similarly, the insulation layers 120b, the metal layers 130b and the vias 140b are formed in the same way recited above. Finally, solder masks 150 are formed over the whole structure, while partially exposing the outmost metal layers 130b for external connection. The exposed portions of the outmost metal layer 130b on a top of the structure are used as bump pads 132, and those on a bottom of the structure are used as ball pads 134.
In accordance with flip-chip ball grid array (FCBGA) packaging, when the bump pitch is less than 240 micron, the layout thereof is limited to 40 micron/40 micron (line width/line pitch) design rule. Since a high-density and small-pitch packaging substrate can be obtained by build-up technology, such a packaging substrate can meet the requirement of a high-pin-count device. Currently, the FCBGA substrate has six layers and is formed by build-up fabrication. The number of build-up layers increases with the circuit density increases. However, the FCBGA substrate has disadvantages of low yield and high production cost.